1. Field
Exemplary embodiments of the present invention relate to technology for fabricating a semiconductor device, and more particularly, to a semiconductor device with a buried bit line and a method for fabricating the same.
2. Description of the Related Art
To increase the amount of memory cells on a chip, patterns may be shrunk. Due to pattern shrinkage, a mask for a mask process may also be smaller in size. Accordingly, a sub-40 nm semiconductor device may adopt an ArF photoresist (PR) layer. However, as an even smaller pattern is desired, the ArF PR layer may not be suitable for a smaller pattern application.
Therefore, a semiconductor device, such as a DRAM memory device, may use 3-dimensional cell formation techniques.
A transistor with a planar channel has a physical limit in a leakage current, an on current, and a short channel effect if the semiconductor device is further miniaturized. Therefore, it is difficult to further miniaturize the semiconductor device. However, a transistor using a vertical channel (hereafter, referred to as a vertical channel transistor) may further miniaturize the semiconductor device.
The vertical channel transistor includes an active region extended vertically over a substrate, a gate electrode (referred to as a vertical gate (VG)) formed on a sidewall of the active region, and a junction formed over and under the active region. The vertical gate is set to be the center of the active region. In such a vertical channel transistor, the vertical gate vertically forms a channel. The lower junction is coupled to a buried bit line (BBL).
FIG. 1 illustrates a conventional semiconductor device.
Referring to FIG. 1, a plurality of bodies 13 isolated by trenches 12 are formed on a substrate 11. The bodies 13 correspond to active regions and extend vertically from the surface of the substrate 11. A hard mask layer 14 is formed on the bodies 13. A junction 16 is formed on one sidewall of each body 13. A dielectric layer 15 is formed on both sidewalls of the body 13. A part of the dielectric layer 15 is selectively removed to form an open portion, which exposes the junction 16. A buried bit line 18 is electrically coupled to the junction 16 through the open portion and partially fills the trench 12. A barrier layer 17 is formed to prevent diffusion between the buried bit line 18 and the junction 16.
In the conventional semiconductor device of FIG. 1, the buried bit line 18 is formed of a metal layer to reduce resistance. In order to form a contact between the junction 16 and the buried bit line 18, a manufacturing process includes a side contact process for exposing one sidewall of the body 13. The side contact process is referred to as a one side contact (OSC) process.
When a metal layer is used as the buried bit line 18, an ohmic contact may be formed to reduce contact resistance with the junction 16, which is formed of single crystal silicon.
The ohmic contact 19 may be formed of a silicide layer.
In this case, however, silicide agglomeration is caused by a thermal process accompanying the silicide process. Such silicide agglomeration may cause a loss of the junction 16, and a junction leakage increases.